The present invention relates to programmable logic networks, i.e. integrated circuits having n logic signal inputs and m outputs, and adapted to supply at each of the outputs a particular programmed logic combination of the binary signals applied to the inputs. This logic combination is expressed in the form of a logic sum of several logic products of the input signals.
In the general case, a programmable logic network has two gate matrices, namely:
on the one hand a product matrix which consists of a series of p logic gates each having 2n inputs; these inputs are coupled to some of the n inputs Ai, complemented or not, of the network, and the outputs of the gates supply signals which are products of the input variables a.sub.i received; these products are designated by the term "intermediate products"; they are p in number if there are p gates; this product matrix is generally called AND and the gates are AND gates or perform the logic equivalent of an AND function;
on the other hand a sum matrix or OR matrix which consists of a series of m gates (as many as there are outputs of the network, i.e. as many as the different logic combinations to be effected); these gates are OR gates, or perform the logic equivalent thereof; they each have p inputs coupled respectively to some of the outputs of the p AND gates of the AND matrix; the outputs of the m OR gates supply logic sums of the signals applied to their inputs, i.e. sums of the products of the input variables. These outputs are the outputs of the network.
The purpose of programming the network is to arrange for each output to define a particular chosen combination of the input variables, expressed in the form of a sum of the products of certain of these variables.
We may digress here to point out that the reasoning would be identical if the positions of the OR and AND matrices were reversed to provide output logic combinations expressed in the form of products of sums. Boole algebra shows that such a reversal is possible without difficulty, and the invention will be merely described for sums of products.
The programming of the network consists then in defining the AND matrix so as to obtain products of some input variables, and to define the OR matrix in order to obtain sums of some of the products obtained.
For example, so as to obtain the combinations EQU S.sub.1 =a.sub.1 a.sub.2 a.sub.3 +a.sub.1 a.sub.2
and EQU S.sub.2 =a.sub.1 a.sub.3 +a.sub.1 a.sub.2
in a network with three inputs and two outputs, it is necessary:
(1) to provide an AND gate receiving aHD 1, a.sub.2 and a.sub.3, another receiving a.sub.1 and aHD 2 and a third receiving a.sub.1 and a.sub.3 ;
(2) to provide an OR gate receiving the output of the first and second AND gates and another receiving the output of the second and third AND gates.
Before programming, the AND gates of the AND matrix may receive all the a.sub.i variable inputs and their complements; after programming they only receive the variables selected for forming a particular product; the others must be disconnected so that there is no influence, on a particular product, of an a.sub.i variable not appearing in this product.
Similarly, the OR gates of the OR matrix may receive, before programming, all the outputs of the AND gates, i.e. they may add up all the p intermediate products calculated by the AND matrix; after programming, an OR gate corresponding to an output of the network must only receive at its inputs the intermediate products appearing in the logic combination to be provided at this output; the outputs of the other AND gates, corresponding to products not appearing in the sum, must be disconnected.
The present invention relates to networks which are electrically programmable by the user and not those which are programmed during manufacture by masking techniques.
The problem to be resolved is the following: the electric programming of the network requires an individual electric access to all the inputs of the AND gates and of the OR gates, a total of 2n.times.p AND gate inputs to which are added p.times.m OR gate inputs. For example, we may have 8 inputs breaking down into 16 with their complements, 8 outputs and 64 intermediate products (the numbers n, m and p are independent and determine the overall capacity of the network). These figures correspond to 1536 programming points to be provided. Each of these points must be individually accessible so as to apply an adequate programming signal (for example an electric voltage capable of destroying a fuse in series with a diode in a particularly simple construction).
The programming seen from the user's side consists in selecting the gate inputs which must receive a neutralizing signal, in applying this signal thereto and in leaving the other inputs active.
If there is a number of programming points as high as 1536, it may be arranged that 11 binary inputs (2.sup.11 =2048) will serve to designate each of the gates through a decoder, so as to direct the programming signal exclusively to the designated gate. It is imperative, so as to minimize the number of external connection pins of the integrated circuit, for these inputs to be taken from the pins necessarily existing on the integrated circuit, for example the pins corresponding to the Ao and An-1 inputs and to the So to Sm-1 outputs, these pins not having in this case the same function in the normal logic computing mode and in the exceptional programming mode (a special input defining the mode).
For the operator, the problem is the following; he must:
establish the formulae of the different logic combinations to be achieved (the different product sums of the a.sub.i input variables); and must assign to each an output of the network, i.e. a given OR gate;
draw up a list of all the intermediate products appearing in the different logic combinations; and he must assign an AND gate to each of them;
determine, for a particular product i.e. for a respective AND gate, which inputs of this AND gate are to be neutralized, taking into account the correspondence between the a.sub.i inputs of the network and the AND gate inputs; this correspondence is direct since each A.sub.i input of the network is connected to a respective input of all the AND gates;
provide, before going over to programming, addressing of each of the inputs to be neutralized, taking into account the correspondence provided by the manufacturer, between the addressing inputs and the inputs of the AND gates to be neutralized; but this time, even if it is the A.sub.i inputs, i.e. the inputs of variables, which also serve as addressing inputs in the programming mode, the correspondence is no longer direct; it takes place through a binary code because of the large number (2n.times.p) of programming points to be addressed in the AND matrix;
after having effected these operations and programmed the whole of the AND matrix, the operator must further determine, for a particular logic combination to be obtained, i.e. for a respective OR gate, which are the inputs of this OR gate which must be neutralized, taking into account the correspondence between the list of the intermediate products which he has drawn up and the OR gate input positions connected to the intermediate product outputs;
finally, the operator must provide, before going on with programming of the OR matrix, addressing for each of the OR gate inputs to be neutralized, taking into account the correspondence provided by the manufacturer, in the programming mode, between the addressing inputs and the OR gate inputs to be disconnected; this correspondence is furthermore obviously quite indirect and the user must know the binary coding thereof; if it is again the inputs of a.sub.i variables which serve as inputs for addressing the OR matrix in the programming mode, that makes an additional correspondence to be known by the programmer between the numbering of external pins of the network and the internal structure thereof.
An example of a programmable logic network using this principle is the circuit IM5200 from the firm INTERSIL, which is electrically programmable; in this circuit, two of the inputs of A.sub.i variables are used to define the changeover to the programming mode, four outputs of the network are used, in the programming mode, to designate AND and OR matrix sectors to be programmed, and nine inputs of variables are used, in the programming mode, to designate the gate inputs to be disconnected.
The very considerable work of the programmer may be justified since it is a non-reprogrammable network. However, it would be desirable, even in this case, to reduce this work; it is in any case necessary to achieve this if the network is electrically erasable and reprogrammable, otherwise the advantage of reprogramming would disappear in face of the difficulty thereof.